3-15 MT8808 8 x 8 analog switch array features internal control latches and address decoder short set-up and hold times wide operating voltage: 4.5v to 13.2v 12vpp analog signal capability ? on 65 ? max. @ v dd =12v, 25 c ? r on 10 ? @ v dd =12v, 25 c full cmos switch for low distortion minimum feedthrough and crosstalk separate analog and digital reference supplies low power consumption iso-cmos technology applications key systems pbx systems mobile radio test equipment /instrumentation analog/digital multiplexers audio/video switching description the zarlink MT8808 is fabricated in zarlink s iso- cmos technology providing low power dissipation and high reliability. the device contains a 8 x 8 array of crosspoint switches along with a 6 to 64 line decoder and latch circuits. any one of the 64 switches can be addressed by selecting the appropriate six address bits. the selected switch can be turned on or off by applying a logical one or zero to the data input. v ss is the ground reference of the digital inputs. the range of the analog signal is from v dd to v ee . ordering information MT8808ae 28 pin plastic dip MT8808ap 28 pin plcc -40 to 85 c figure 1 - functional block diagram 6 to 64 decoder latches 8 x 8 switch array ax0 ax1 ay0 ay1 ay2 strobe data reset vdd vee vss xi i/o (i=0-7) yi i/o (i=0-7) 11 64 64 ?????????????????? ??????????????? ax2 issue 3 march 1997 iso-cmos
MT8808 iso-cmos 3-16 figure 2 - pin connections pin description pin # name description 1ay2 ay2 address line (input) . 2 strobe strobe (input) : enables function selected by address and data. address must be stable before strobe goes high and data must be stable on the falling edge of the strobe. active high. 3v ee negative power supply. 4 data data (input) : a logic high input will turn on the selected switch and a logic low will turn off the selected switch. active high. 5v ss digital ground reference . 6-9 x0, x2, x4, x6 x0, x2, x4 and x6 analog (inputs/outputs): these are connected to the x0, x2, x4 and x6 rows of the switch array. 10 reset master reset (input): this is used to turn off all switches. active high. 11-18 y7 - y0 y7 - y0 analog (inputs/outputs): these are connected to the y0 - y7 columns of the switch array. 19 v dd positive power supply. 20-23 x7, x5, x3, x1 x7, x5, x3 and x1 analog (inputs/outputs): these are connected to the x7, x5, x3 and x1 rows of the switch array. 24-26 ax0- ax2 ax0 - ax2 address lines (inputs) . 27,28 ay0, ay1 ay0 and ay1 address lines (inputs) . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 ay2 strobe vee data vss x0 x2 x4 x6 reset y7 y6 y5 y4 ay1 ay0 ax2 ax1 ax0 x1 x3 x5 x7 vdd y0 y1 y2 y3 28 pin plastic dip 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 ? data ax1 ax0 x1 x3 x5 x7 vdd vss x0 x2 x4 x6 reset y7 y1 3 2 1 28 27 26 12 13 14 15 16 17 18 vee strob e a y2 ay1 ay0 ax2 y6 y5 y4 y3 y2 y0 28 pin plcc
iso-cmos MT8808 3-17 functional description the MT8808 is an analog switch matrix with an array size of 8 x 8. the switch array is arranged such that there are 8 columns by 8 rows. the columns are referred to as the y inputs/outputs and the rows are the x inputs/outputs. the crosspoint analog switch array will interconnect any x i/o with any y i/o when turned on and provide a high degree of isolation when turned off. the control memory consists of a 64 bit write only ram in which the bits are selected by the address inputs (ay0-ay2, ax0-ax2). data is presented to the memory on the data input. data is asynchro-nously written into memory whenever the strobe input is high and is latched on the falling edge of strobe. a logical ? written into a memory cell turns the corresponding crosspoint switch on and a logical ? turns the crosspoint off. only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. the remaining switches retain their previous states. any combination of x and y inputs/ outputs can be interconnected by establishing appropriate patterns in the control memory. a logical ? on the reset input will asynchronously return all memory locations to logical ? turning off all crosspoint switches. two voltage reference pins (v ss and v ee ) are provided for the MT8808 to enable switching of negative analog signals. the range for digital signals is from v dd to v ss while the range for analog signals is from v dd to v ee . v ss and v ee pins can be tied together if a single voltage reference is needed. address decode the six address inputs along with the strobe are logically anded to form an enable signal for the resettable transparent latches. the data input is buffered and is used as the input to all latches. to write to a location, reset must be low while the address and data are set up. then the strobe input is set high and then low causing the data to be latched. the data can be changed while strobe is high, however, the corresponding switch will turn on and off in accordance with the data input. data must be stable on the falling edge of strobe in order for correct data to be written to the latch.
MT8808 iso-cmos 3-18 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? dc electrical characteristics are over recommended temperature range. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ee unless otherwise stated. parameter symbol min max units 1 supply voltage v dd v ss -0.3 -0.3 15.0 v dd +0.3 v v 2 analog input voltage v ina -0.3 v dd +0.3 v 3 digital input voltage v in v ss -0.3 v dd +0.3 v 4 current on any i/o pin i 15 ma 5 storage temperature t s -65 +150 c 6 package power dissipation plastic dip p d 0.6 w recommended operating conditions - voltages are with respect to v ee unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t o -40 25 85 c 2 supply voltage v dd v ss 4.5 v ee 13.2 v dd -4.5 v v 3 analog input voltage v ina v ee v dd v 4 digital input voltage v in v ss v dd v dc electrical characteristics ? - voltages are with respect to v ee =v ss =0v, v dd =12v unless otherwise stated. characteristics sym min typ max units test conditions 1 quiescent supply current i dd 1 100 a all digital inputs at v in =v ss or v dd 0.4 1.5 ma all digital inputs at v in =2.4 + v ss ; v ss =7.0v 5 15 ma all digital inputs at v in =3.4v 2 off-state leakage current (see g.9 in appendix) i off 1 500 na iv xi - v yj i = v dd - v ee see appendix, fig. a.1 3 input logic ? level v il 0.8+v s s vv ss =7.5v; v ee =0v 4 input logic ? level v ih 2.0+v ss vv ss =6.5v; v ee =0v 5 input logic ? level v ih 3.3 v 6 input leakage (digital pins) i leak 0.1 10 a all digital inputs at v in = v ss or v dd dc electrical characteristics- switch resistance - v dc is the external dc offset applied at the analog i/o pins. characteristics sym 25 c70 c85 c units test conditions typ max typ max typ max 1 on-state v dd =12v resistance v dd =10v v dd = 5v (see g.1, g.2, g.3 in appendix) r on 45 55 120 65 75 185 75 85 215 80 90 225 ? ? ? v ss =v ee =0v,v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2 2 difference in on-state resistance between two switches (see g.4 in appendix) ? r on 510 10 10 ? v dd =12v, v ss =v ee =0, v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2
iso-cmos MT8808 3-19 ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. crosstalk measurements are for plastic dips only, crosstalk values for plcc packages are approximately 5db better. ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. digital input rise time (tr) and fall time (tf) = 5ns. typical ?ures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. ? refer to appendix, fig. a.7 for test circuit. ac electrical characteristics ? - crosspoint performance -voltages are with respect to v dd =5v, v ss =0v, v ee =-7v, unless otherwise stated. characteristics sym min typ max units test conditions 1 switch i/o capacitance c s 20 pf f=1 mhz 2 feedthrough capacitance c f 0.2 pf f=1 mhz 3 frequency response channel ?n 20log(v out /v xi )=-3db f 3db 45 mhz switch is ?n? v ina = 2vpp sinewave; r l = 1k ? see appendix, fig. a.3 4 total harmonic distortion (see g.5, g.6 in appendix) thd 0.01 % switch is ?n? v ina = 2vpp sinewave f= 1khz ; r l =1k ? 5 feedthrough channel ?ff feed.=20log (v out /v xi ) (see g.8 in appendix) fdt -95 db all switches ?ff? v ina = 2vpp sinewave f= 1khz; r l = 1k ? . see appendix, fig. a.4 6 crosstalk between any two channels for switches xi-yi and xj-yj. xtalk=20log (v yj /v xi ). (see g.7 in appendix). x talk -45 db v ina =2vpp sinewave f= 10mhz; r l = 75 ? . -90 db v ina =2vpp sinewave f= 10khz; r l = 600 ? . -85 db v ina =2vpp sinewave f= 10khz; r l = 1k ? . -80 db v ina =2vpp sinewave f= 1khz; r l = 10k ? . refer to appendix, fig. a.5 for test circuit. 7 propagation delay through switch t ps 30 ns r l =1k ? ; c l =50pf ac electrical characteristics ? - control and i/o timings - voltages are with respect to v dd =5v, v ss =0v, v ee =-7v, unless otherwise stated. characteristics sym min typ max units test conditions 1 control input crosstalk to switch (for cs, data, strobe, address) cx talk 30 mvpp v in =3v squarewave; r in =1k ? , r l =10k ? . see appendix, fig. a.6 2 digital input capacitance c di 10 pf f=1mhz 3 switching frequency f o 20 mhz 4 setup time data to strobe t ds 10 ns r l = 1k ? , c l =50pf ? 5 hold time data to strobe t dh 10 ns r l = 1k ? , c l =50pf ? 6 setup time address to strobe t as 10 ns r l = 1k ? , c l =50pf ? 7 hold time address to strobe t ah 10 ns r l = 1k ? , c l =50pf ? 8 strobe pulse width t spw 20 ns r l = 1k ? , c l =50pf ? 9 reset pulse width t rpw 40 ns r l = 1k ? , c l =50pf ? 10 strobe to switch status delay t s 40 100 ns r l = 1k ? , c l =50pf ? 11 data to switch status delay t d 50 100 ns r l = 1k ? , c l =50pf ? 12 reset to switch status delay t r 35 100 ns r l = 1k ? , c l =50pf ?
MT8808 iso-cmos 3-20 figure 3 - control memory timing diagram * see appendix, fig. a.7 for switching waveform table 1. address decode truth table ay2 ay1 ay0 ax2 ax1 ax0 connection ay2 ay1 ay0 ax2 ax1 ax0 connection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y0 x1 y0 x2 y0 x3 y0 x4 y0 x5 y0 x6 y0 x7 y0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y4 x1 y4 x2 y4 x3 y4 x4 y4 x5 y4 x6 y4 x7 y4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y1 x1 y1 x2 y1 x3 y1 x4 y1 x5 y1 x6 y1 x7 y1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y5 x1 y5 x2 y5 x3 y5 x4 y5 x5 y5 x6 y5 x7 y5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y2 x1 y2 x2 y2 x3 y2 x4 y2 x5 y2 x6 y2 x7 y2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y6 x1 y6 x2 y6 x3 y6 x4 y6 x5 y6 x6 y6 x7 y6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y3 x1 y3 x2 y3 x3 y3 x4 y3 x5 y3 x6 y3 x7 y3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y7 x1 y7 x2 y7 x3 y7 x4 y7 x5 y7 x6 y7 x7 y7 t rpw t spw t as t ah t dh t d t s t r t r t ds 50% 50% 50% 50% 50% 50% 50% 50% 50% reset strobe address data switch* on off
MT8808 iso-cmos 3-21
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at
|
